Modeling, Identification, and Compensation of Channel Mismatch Errors in Time-Interleaved ADCs

Modern signal processing applications emerging in telecommunication and instrumentation industries need high-speed analog-to-digital converters (ADCs), which can be achieved by employing a time-interleaved parallel array of ADCs (time-interleaved ADCs). The time interleaving of the channels allows to increase the sampling rate by the number of channels compared to a single channel. Unfortunately, time-interleaved ADCs suffer from channel mismatches that limit their performance, wherefore this thesis deals with the identification and compensation of channel mismatches in time-interleaved ADCs. By using nonlinear hybrid filter banks, we have modeled and analyzed channel mismatches in detail. The model covers linear and nonlinear channel mismatches, unifies, and extends the channel models found in the literature. A novel foreground channel mismatch identification method has been developed, which can be used to fully characterize dynamic linear mismatches. A background identification method provides accurate timing mismatch estimates. Finally, power-efficient channel mismatch compensation methods, which significantly reduce the impact of channel mismatches on the time-interleaved ADC performance, are presented in this work. Thanks to the presented methods, it will be possible to use high-rate timeinterleaved ADCs for power-critical as well as for high-precision applications.